D.c. to a.c. converter for use with battery driven clocks and the like



Get. 21, 1959 c, MERRELL 3,474,352

0.0. T0 A.C. CONVERTER FOR USE WITH BATTERY DRIVEN 01400145 AND THE LIKE] Filed Nov. 22, 1967 A 16 RS i RB C T Vc R R TA J l] l INVENTOR KENNETH c. MERRELL ATTORNEYS United States Patent.

3,474,352 D.C. TO A.C. CONVERTER FOR USE WITH gAg'IgERY DRIVEN CLOCKS AND THE II Kenneth C. Merrell, Brea, Calif., assignor to Robertshaw Controls Company, Richmond, Va., a corporation of Delaware Filed Nov. 22, 1967, Ser. No. 685,088 Int. Cl. H03k 3/26 US. Cl. 331-111 6 Claims ABSTRACT OF THE DISCLOSURE A transistorized DC. to pulse converter in which the pulse period is substantially independent of supply voltage and transistor parameters.

DC. to pulse converters are useful in driving alternating current synchronous timing or clock motors from a battery or a DC. source. In the present invention the converter is substantially insensitive to variations in ambient temperature and in supply voltage.

The invention comprises an RC charging circuit and a voltage divider connected in parallel across a source of DC. voltage. A transistorized switching arrangement provides a minimum and maximum threshold to the voltage built up across the capacitor whereby the transistors discharge the capacitor when the voltage thereacross reaches some preset maximum value. The discharge path is then closed when the voltage across the capacitor reaches some preset minimum value. The capacitor charges substantially between zero and the value determined by the voltage divider.

The invention will be better understood by referring to the following detailed description and the accompanying drawings wherein,

FIGURE 1 is a schematic diagram of a preferred embodiment of the invention; and

FIGURES 2A and 2B are waveforms illustrating voltages occurring at different points within the schematic of FIGURE 1.

The circuitry shown in FIGURE 1 operates to convert a DC voltage into a train of positive pulses at the output terminal 20. The pulse repetition rate is substantially independent of variation in the supply source and in transistor parameters. A Zener diode 10 and series resistor RS connected across the supply source B+ provides a voltage V to the converter circuitry.

The circuit initial conditions are as follows:

Q and Q are non-conducting Q is conducting.

The transistor Q is off because the base-emitter junction is reverse biased, and Q is on because V is lower than the base potential of Q As C begins charging through resistor R, the emitter potential of Q begins to drop until it drops low enough to turn on Q When Q turns on, it pulls Q into saturation thereby short circuiting R and raising the potential at the output. The capacitor C discharges quickly through Q and Q down to a value sufficient to turn ofi Q thereby turning ofi Q and beginning the cycle again.

The voltage across capacitor C is illustrated by the waveform of FIGURE 2A and the output voltage V is illustrated by the waveform of FIGURE 2B. The maxi- 3,474,352 Patented Oct. 21, 1 969 ice mum voltage attained across capacitor C is that which occurs just as Q turns on and can be written as The minimum voltage attained across the capacitor during the rapid discharge is that which occurs just as Q turns off and can be written as Since the discharge time is substantially instantaneous the total period is substantially equal to the time it takes to change capacitor C from a minimum value of V min. to a maximum value of V max. The period T may be expressed as V,-V., (min.)] V,-V. (max.) RC

As the saturation voltage of Q approaches zero and when V Q =V Q the equation for T becomes,

Thus, the period of the output pulse train is reasonably independent of the supply voltage or transistor parameters. The Zener diode and series resistor R further improves the frequency independence with supply voltage and allows operation over supply variations of 50%.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A DC. to pulse converter comprising:

(a) a source of DC. potential,

(b) a capacitor and resistor connected in series across said source,

(0) a voltage divider network comprising first and second impedance means connected across said source,

(d) first and second transistors having their bases connected together and their emitters connected respectively to the junction of said resistor and capacitor and the junction of said first and second impedance means,

(e) means for biasing said first transistor non-conducting until the voltage on said capacitor reaches a maximum value proportional to said supply voltage,

(f) switch means responsive to said first transistor conducting for providing a discharge path for said ca pacitor and for causing said first transistor to turn off when the voltage across said capacitor is reduced to a minimum value independent of said supply voltage.

2. A DC to pulse converter as claimed in claim 1 wherein said switch means comprises a third transistor, said third transistor having its emitter collector path connected across said first impedance means and its base connected to the collector of said first transistor.

3. A DC. to pulse converter as claimed in claim 2 wherein said second transistor has its collector connected to its base.

4. A DC. to pulse converter as claimed in claim 3 wherein said first and second transistors are NPN type transistors.

o 4 5. A DC to pulse converter as claimed in claim 4 References Cited wherein said third transistor is a PNP type transistor. Wirel World 397 Au t 1965 6. A DC. to pulse converter as claimed in claim 5 655 gus wherein said source of DC. potential comprises an un- JOHN KOMINSKI, primary Examiner regulated DC. voltage source, a series resistor, and a 5 Zener diode connected across the series combination of US. Cl. X.R.

said unregulated voltage source and said series resistor. 307-288; 331-l08 

